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3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Table 3. Alarm Mask Bits
AM4
1
1
1
1
0
AM3
1
1
1
0
0
AM2
1
1
0
0
0
AM1
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
When the RTC register values match alarm register set-
tings, the alarm flag (AF) is set to a 1. If AE is also a 1,
the alarm condition activates the IRQ /FT output. When
CS is active, the IRQ /FT signal can be cleared by hold-
ing the FLAGS register address stable for t RC and forc-
ing either OE or WE active (see Figure 1). The flag does
not change state until the end of the read/write cycle
and after the IRQ /FT signal has deasserted. To avoid
inadvertently clearing the IRQ /FT signal while preparing
The IRQ /FT output can also be activated during battery
backup mode. The IRQ /FT goes low if an alarm occurs
and both AE and ABE are set to 1. The AE and ABE
bits are reset to 0 during the power-up transition, but an
alarm generated during power-up will set AF to a 1.
Therefore, the AF bit can be read after system power-
up to determine if an alarm was generated during the
power-up sequence. Figure 3 illustrates alarm timing
during battery backup mode and power-up states.
for subsequent write/read cycles at other register
addresses, assure that t AW is met for that subsequent
address (see Figure 2).
CE
WE OR OE
CS
t RC MAX
A0 – A3
IRQ/FT
Figure 1. Clearing Active IRQ Waveforms
ADDRESS 0h
HIGH
IMPEDANCE
14
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